The present invention relates to a phase and frequency-locked loop (P/FLL) circuit, and more particularly to the expansion of the pull-in range of the frequency and the reduction of the synchronization time thereof.
A P/FLL circuit, intended for feedback-control of a voltage controlled oscillator (VCO) to cause the same to output signals synchronized with input signals in phase and frequency, has a configuration in which a phase comparator, a loop filter and the VCO are connected in a loop form. The phase comparator, receiving input signals and the output signals of the VCO (the output of the P/FLL circuit), generate voltages corresponding to the phase differences as phase difference signals. The loop filter removes the high frequency noise component from the phase difference signals to output a frequency control signal, and also determines the response characteristics and the synchronization characteristics of the P/FLL circuit according to its amplitude and phase characteristics. The VCO oscillates at a frequency in accordance with the frequency control signal, with a predetermined oscillation frequency range. The oscillation output of the VCO is fed back to the phase comparator, and is also supplied as the output signal of the P/FLL circuit.
In such a P/FLL circuit, the process in which an output signal synchronized with an input signal is obtained can be divided into a frequency pull-in process and a phase lock-in process following it. Usually, an input signal and the output signal of a VCO in a free-running system are not identical either in frequency or in phase. Therefore, after their frequencies are brought close to each other, they are synchronized in the lock-in process. Since a cycle slip (rotation of the phase difference) is repeated in the pull-in process, the output of the phase comparator takes on a beat waveform. The D.C. component of this beat signal is used as the control signal of the VCO. If the frequency of the beat signal is not higher than a frequency determined by the loop characteristic of the P/FLL circuit, synchronization with the input signal will be possible. In the pull-in process, the positive half-cycle acts to bring the oscillation frequency of the VCO closer to, and the negative half-cycle, to bring it away from, the frequency of the input signal. As a result, in the beat waveform, the positive half-cycle gradually becomes longer than the negative half-cycle and, as the D.C. component increases, the oscillation frequency of the VCO comes closer to the frequency of the input signal. In such a P/FLL circuit by the prior art, there is the problem that the pull-in process takes a long time.